Conventionally, a semiconductor device such as a flash memory or dynamic memory is such that the voltage necessary for internal operation is generated within the semiconductor device so that such operations as write, read and erase of stored content may be performed. To accomplish this, the semiconductor device is provided internally with a booster circuit that includes charge pump units. A problem encountered, however, is a large peak consumption current that develops in the booster circuit at the time of start-up and a power supply voltage that fluctuates. Many improvements have been made heretofore.
An example of such an improvement is to reduce the voltage amplitude of a boot-up signal immediately after input of the start-up signal of the booster circuit and then enlarge the voltage amplitude of the boot-up signal upon elapse of a fixed period of time measured by a timer circuit, thereby suppressing peak consumption current at start-up of the booster circuit (see FIGS. 1 and 5 in the specification of Japanese Patent Kokai Publication No. JP-P2003-244949A).
FIG. 8 illustrates another example of the prior art. This example comprises charge pump units 1, 2, 3, 4 each having a clock buffer and charge pump circuit, a clock generating circuit 5, a capacitor 8, dividing unit 19 for dividing boosted voltage, and, comparison unit 10. A boosted voltage Vpp is output to an output terminal 9, whence the voltage is supplied to a booster circuit load 20 within a semiconductor device.
Operation will be described with reference to FIG. 8. If a booster circuit activating signal TACT that enters from a terminal 6 is activated and a divided booster voltage VDIV0 obtained by dividing the boosted voltage Vpp is smaller than a reference voltage VREF, then the clock generating circuit 5 generates a clock pulse in response to a clock generation control signal, which is the output of the comparison unit 10. A clock pulse 51 is supplied to clock buffer #1 of the charge unit 1, whereby charge pump circuit #1 starts boosting voltage.
The clock generating circuit 5 successively generates clock pulses 52, 53, 54 of different phases and supplies these pulses to clock buffers #2, #3, #4, respectively, whereby all of the charge pump units 2, 3, 4 start a voltage boosting operation in sync with respective ones of these clock pulses of different phases. If the divided booster voltage VDIV0 is greater than the reference voltage VREF, then the clock generating circuit 5 stops supplying clock pulses, thereby halting the boosting operation of all of the charge pump units.
In general, the current supply capability of a charge pump is proportional to the clock-pulse cycle. If the clock pulses are high in speed, then the current supply capability is high. Generally speaking, in order to assure a sufficiently high current supply capability without increasing the area of a booster circuit, use is made of clock pulses of higher speed, e.g., a pulse cycle on the order of tens of nanoseconds. Merely making the phases of these clock pulses different from one another cannot assure that the phase difference necessary to suppress fluctuation of the power supply voltage will be obtained. Accordingly, even if ripple of the power supply voltage can be mitigated merely by making the phases of the clock pulses different from one another, this will not be sufficient to suppress peak current at start-up of the booster circuit and to suppress fluctuation of the power supply voltage.
[Patent Publication 1]
    JP Patent Kokai Publication No. JP-P2003-244940A